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FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
Table 13: Stretch Memory Cycle Width
CKCON[2:0]
Stretch
Value
Read Signal Width
memaddr memrd
Write Signal Width
memaddr memwr
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
1.4.4
71M6533/71M6534-Specific Special Function Registers
Table 14: 71M6533/71M6534 Specific SFRs
I C EEPROM interface data register.
Register
(Alternate Name)
EEDATA
EECTRL
ERASE
(FLSH_ERASE)
FL_BANK [2:0]
PGADDR
(FLSH_PGADR)
SFR
Address
0x9E
0x9F
0x94
0xB6[2:0]
0xB7
0xB2[0]
Bit Field
Name
FLSH_PWE
R/W
R/W
R/W
W
R/W
R/W
R/W
Description
2
I 2 C EEPROM interface control register.
See Section 1.5.10 EEPROM Interface for a
description of the command and status bits
available for EECTRL .
This register is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle.
See the Flash Memory section for details.
Flash Bank Selection.
Flash Page Erase Address register. Contains
the flash memory page address (page 0
through page 127) that will be erased during the
Page Erase cycle (default = 0x00). Must be re-
written for each new Page Erase cycle.
Program Write Enable:
0: MOVX commands refer to XRAM Space,
normal operation (default).
1: MOVX @DPTR,A moves A to Program
Space (Flash) @ DPTR.
0: Mass Erase disabled (default).
1: Mass Erase enabled.
Protects flash from address CE_LCTN *1024 to
the end of memory from flash page erase.
Protects flash from address 0 to address
BOOT_SIZE *1024 from flash page erase.
FLSHCRL
Rev 2
Mass Erase Enable:
0xB2[1] FLSH_MEEN W
Must be re-written for each new Mass Erase cycle.
0xB2[4] WRPROT_CE*
0xB2[5] WRPROT_BT*
0xB2[6] SECURE R/W Enables security provisions that prevent external
reading of flash memory and CE program RAM.
This bit is reset on chip reset and may only be set.
Attempts to write zero are ignored.
0xB2[7] PREBOOT R Indicates that the preboot sequence is active.
* The WRPROT_CE and WRPROT_BT bits can only be cleared when the SECURE bit
is not set. When SECURE = 1, WRPROT_CE and WRPROT_BT can only be set to 1.
A hardware reset is required to clear these bits if SECURE = 1.
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